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1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
1Mb SYNCBURSTTM SRAM
FEATURES
* Fast clock and OE# access times * Single +3.3V +0.3V/-0.165V power supply (VDD) * Separate +3.3V +0.3V/-0.165V isolated output buffer supply (VDDQ) * SNOOZE MODE for reduced-power standby * Common data inputs and data outputs * Individual BYTE WRITE control and GLOBAL WRITE * Three chip enables for simple depth expansion and address pipelining * Clock-controlled and registered addresses, data I/Os and control signals * Internally self-timed WRITE cycle * Burst control pin (interleaved or linear burst) * Automatic power-down for portable applications * 100-lead TQFP package for high density, high speed * Low capacitive bus loading * x18, x32 and x36 versions available
MT58L64L18F, MT58L32L32F, MT58L32L36F
3.3V VDD, 3.3V I/O, Flow-Through
100-Pin TQFP*
*JEDEC-standard MS-026 BHA (LQFP).
OPTIONS
* Timing (Access/Cycle/MHz) 7.5ns/8.8ns/113 MHz 8.5ns/10ns/100 MHz 10ns/15ns/66 MHz * Configurations 64K x 18 32K x 32 32K x 36 * Package 100-pin TQFP * Operating Temperature Range Commercial (0C to +70C) Industrial (-40C to +85C)
Part Number Example:
MARKING
-7.5 -8.5 -10 MT58L64L18F MT58L32L32F MT58L32L36F T None IT
MT58L32L36FT-10 IT
GENERAL DESCRIPTION
The Micron(R) SyncBurstTM SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The MT58L64L18F and MT58L32L32/36F 1Mb SRAMs integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-trig1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
gered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#). Asynchronous inputs include the output enable (OE#), snooze enable (ZZ) and clock (CLK). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa pins and DQPa; BWb#
1
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM 64K x 18
16 SA0, SA1, SA MODE ADV# CLK ADDRESS REGISTER 16 14 16
2
SA0-SA1 SA1'
BINARY Q1 COUNTER AND LOGIC CLR Q0
SA0'
ADSC# ADSP# BYTE "b" WRITE REGISTER 9 BYTE "b" WRITE DRIVER 9 64K x 9 x 2 MEMORY ARRAY 9 18 SENSE 18 AMPS OUTPUT BUFFERS 18
BWb#
BWa# BWE# GW# CE# CE2 CE2# OE#
BYTE "a" WRITE REGISTER
9
BYTE "a" WRITE DRIVER
DQs DQPa DQPb
ENABLE REGISTER
18
INPUT REGISTERS
2
FUNCTIONAL BLOCK DIAGRAM 32K x 32/36
15 SA0, SA1, SA MODE ADV# CLK BINARY Q1 SA1' COUNTER AND LOGIC Q0 CLR SA0' ADDRESS REGISTER 15 SA0-SA1 13 15
ADSC# ADSP# BWd#
BYTE "d" WRITE REGISTER BYTE "c" WRITE REGISTER
BYTE "d" WRITE DRIVER BYTE "c" WRITE DRIVER BYTE "b" WRITE DRIVER BYTE "a" WRITE DRIVER
INPUT REGISTERS 32K x 8 x 4 (x32) 32K x 9 x 4 (x36) SENSE AMPS OUTPUT BUFFERS
BWc#
DQs
BWb#
BYTE "b" WRITE REGISTER
MEMORY ARRAY
BWa# BWE# GW# CE# CE2 CE2# OE#
BYTE "a" WRITE REGISTER
ENABLE REGISTER 4
NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and timing diagrams for detailed information.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions. Micron's 1Mb SyncBurst SRAMs operate from a +3.3V power supply, and all inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium(R), 680X0 and PowerPC systems and systems that benefit from a very wide data bus. The device is also ideal in generic 16-, 18-, 32-, 36-, 64- and 72-bit-wide applications. Please refer to the Micron Web site (www.micron.com/mti/msp/html/sramprod.html) for the latest data sheet.
TQFP PIN ASSIGNMENT TABLE
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x32/x36 NC/DQPc** DQc DQc VDDQ VSS NC DQc NC DQc DQb DQc DQb DQc VSS VDDQ DQb DQc DQb DQc VSS VDD NC VSS DQb DQd DQb DQd VDDQ VSS DQb DQd DQb DQd DQPb DQd NC DQd x18 NC NC NC PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x18 x32/x36 VSS VDDQ NC DQd NC DQd NC NC/DQPd** MODE SA SA SA SA SA1 SA0 DNU DNU VSS VDD DNU DNU SA SA SA SA SA NC/SA* NC/SA* PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x32/x36 NC/DQPa** DQa DQa VDDQ VSS NC DQa NC DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD NC VSS DQa DQb DQa DQb VDDQ VSS DQa DQb DQa DQb DQPa DQb NC DQb x18 NC NC NC PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 x18 x32/x36 VSS VDDQ DQb DQb NC/DQPb** SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA
NC NC SA
NC NC
* Pins 49 and 50 are reserved for address expansion. ** No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
PIN ASSIGNMENT (Top View) 100-Pin TQFP (D-1)
SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
NC/SA* NC/SA* SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE
SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC/DQPb** DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC/DQPa**
NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC
x32/x36
NC/SA* NC/SA* SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE
* Pins 49 and 50 are reserved for address expansion. **No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
NC/DQPc** DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQPd**
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18 x32/x36 SYMBOL SA0 SA1 SA TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 37 37 36 36 32-35, 44-48, 32-35, 44-48, 80-82, 99, 81, 82, 99, 100 100 93 94 - - 93 94 95 96
BWa# BWb# BWc# BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36 versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on the x18 and x36 versions. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-, 32- or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH.
87
87
BWE#
Input
88
88
GW#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
97
97
CE2
Input
86 83
86 83
OE# ADV#
Input Input
84
84
ADSP#
Input
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18 85 x32/x36 85 SYMBOL ADSC# TYPE Input DESCRIPTION Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. Mode: This input selects the burst sequence. A LOW on this pin selects "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not alter input state while device is operating. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored.
31
31
MODE
Input
64
64
ZZ
Input
(a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72, 73 (b) 8, 9, 12, (b) 68, 69, 13, 18, 19, 22, 72-75, 78, 79 23 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 74 24 - - 51 80 1 30
DQa
DQb
Input/ SRAM Data I/Os: For the x18 version, Byte "a" is DQa pins; Byte "b" Output is DQb pins. For the x32 and x36 versions, Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge of CLK.
DQc DQd NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDD VDDQ VSS NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these pins are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd.
15, 41, 65, 91 15, 41, 65, 91 4, 11, 20, 27, 4, 11, 20, 27, 54, 61, 70, 77 54, 61, 70, 77 5, 10, 14, 17, 5, 10, 14, 17, 21, 26, 40, 55, 21, 26, 40, 55, 60, 67, 71, 76, 60, 67, 71, 76, 90 90 38, 39, 42, 43 38, 39, 42, 43 1-3, 6, 7, 16, 25, 28-30, 51-53, 56, 57, 66, 75, 78, 79, 95, 96 49, 50 16, 66
Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Ground: GND.
DNU NC
- -
Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation.
49, 50
NC/SA
-
No Connect: These pins are reserved for address expansion.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
6
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRSTADDRESS(EXTERNAL) X...X00 X...X01 X...X10 X...X11 SECONDADDRESS(INTERNAL) X...X01 X...X00 X...X11 X...X10 THIRDADDRESS(INTERNAL) X...X10 X...X11 X...X00 X...X01 FOURTHADDRESS(INTERNAL) X...X11 X...X10 X...X01 X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRSTADDRESS(EXTERNAL) X...X00 X...X01 X...X10 X...X11 SECONDADDRESS(INTERNAL) X...X01 X...X10 X...X11 X...X00 THIRDADDRESS(INTERNAL) X...X10 X...X11 X...X00 X...X01 FOURTHADDRESS(INTERNAL) X...X11 X...X00 X...X01 X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
FUNCTION READ READ WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE All Bytes GW# H H H H H L BWE# H L L L L X BWa# X H L H L X BWb# X H H L L X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION READ READ WRITE Byte "a" WRITE All Bytes WRITE All Bytes GW# H H H H L BWE# H L L L X BWa# X H L L X BWb# X H H L X BWc# X H H L X BWd# X H H L X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
7
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
TRUTH TABLE
ADDRESS CE# CE2# CE2 USED Deselected Cycle, Power-Down None H X X Deselected Cycle, Power-Down None L X L Deselected Cycle, Power-Down None L H X Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None SNOOZE MODE, Power-Down None READ Cycle, Begin Burst External READ Cycle, Begin Burst External WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst External External External Next Next Next Next Next Next Current Current Current Current Current Current L L X L L L L L X X H H X H X X H H X H X H X L L L L L X X X X X X X X X X X X L X X H H H H H X X X X X X X X X X X X OPERATION ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP# ADSC# ADV# WRITE# OE# X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
NOTE: 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH. 3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables WRITEs to DQc pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
8
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS ............................... -0.5V to +4.6V VIN -0.5V to VDDQ + 0.5V Storage Temperature (plastic) ............ -55C to +150C Junction Temperature** ................................... +150C Short Circuit Output Current ........................... 100mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C TA +70C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA CONDITIONS SYMBOL VIH VIL ILI ILO VOH VOL VDD VDDQ MIN 2.0 -0.3 -1.0 -1.0 2.4 - 3.135 3.135 MAX VDD + 0.3 0.8 1.0 1.0 - 0.4 3.6 VDD UNITS V V A A V V V V NOTES 1, 2 1, 2 3
1, 4 1, 4 1 1, 5
NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKC /2 for I 20mA Undershoot: VIL -0.7V for t tKC /2 for I 20mA Power-up: VIH +3.6V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the stated DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
9
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(0C TA +70C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) MAX DESCRIPTION Power Supply Current: Operating Power Supply Current: Idle CONDITIONS Device selected; All inputs VIL or VIH; Cycle time tKC MIN; VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, ADV#, GW#, BWx# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC MIN; Outputs open Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, ADV#, GW#, BWx# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC MIN SYMBOL TYP IDD 65 -7.5 245 -8.5 225 -10 150 UNITS NOTES mA 1, 2, 3
IDD1
20
65
65
50
mA
1, 2, 3
CMOS Standby
ISB2
0.5
10
10
10
mA
2, 3
TTL Standby
ISB3
6
25
25
25
mA
2, 3
Clock Running
ISB4
20
65
65
50
mA
2, 3
CAPACITANCE
DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS TA = 25C; f = 1 MHz; VDD = 3.3V SYMBOL CI CO CA CCK TYP 2.7 4 2.5 2.5 MX A 3.5 5 3.5 3.5 UNITS pF pF pF pF NOTES 4 4 4 4
TQFP THERMAL RESISTANCE
DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. SYMBOL JA JC TYP 40 8 UNITS NOTES C/W C/W 4 4
NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 3. Typical values are measured at 3.3V, 25C and 15ns cycle time. 4. This parameter is sampled.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
10
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0C TA +70C; VDD, VDDQ = +3.3V +0.3V/-0.165V)
DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Byte write enables (BWa#-BWd#, GW#, BWE#) Data-in Chip enable (CE#) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Byte write enables (BWa#-BWd#, GW#, BWE#) Data-in Chip enable (CE#) NOTE: 1. 2. 3. 4. 5. 6. SYMBOL
tKC fKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH
MIN 8.8
-7.5 MAX
MIN 10.0
-8.5 MAX
-10 MIN 15 MAX UNITS ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
113 1.9 1.9 7.5 1.5 1.5 4.2 4.2 0 4.2 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 0 3.0 4.0 1.9 1.9
100 4.0 4.0 8.5 3.0 4.0 5.0 5.0 0 5.0 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5
66
2 2
10.0
5.0 5.0 5.0
3 3, 4, 5, 6 3, 4, 5, 6 7 3, 4, 5, 6 3, 4, 5, 6 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9
Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted. Measured as HIGH above VIH and LOW below VIL. This parameter is measured with output loading shown in Figure 2. This parameter is sampled. Transition is measured 500mV from steady state voltage. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough discussion on these parameters. 7. OE# is a "Don't Care" when a byte write enable is sampled LOW. 8. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW for the required setup and hold times. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
11
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
AC TEST CONDITIONS
Input pulse levels ................. VIH = (VDD/2.2) + 1.5V .................... VIL = (VDD/2.2) - 1.5V Input rise and fall times ..................................... 1ns Input timing reference levels ..................... VDD/2.2 Output reference levels ............................ VDDQ/2.2 Output load ............................. See Figures 1 and 2 Figure 1
OUTPUT LOAD EQUIVALENT
Q Z O= 50 50 VT = 1.5V
+3.3V
LOAD DERATING CURVES
The Micron 64K x 18, 32K x 32, and 32K x 36 SyncBurst SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves.
Q 351
317 5pF
Figure 2
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
12
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any access pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current
NOTE: 1. This parameter is sampled.
CONDITIONS ZZ VIH
SYMBOL ISB2Z
tZZ tRZZ tZZI tRZZI
MIN
MAX 10
tKC
UNITS mA ns ns ns ns
NOTES 1 1 1 1
tKC tKC
0
SNOOZE MODE WAVEFORM
CLK
tZZ tRZZ
ZZ I
tZZI
SUPPLY
I SB2
tRZZI
ALL INPUTS*
* Except ZZ
DON'T CARE
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
READ TIMING
tKC
CLK
tKH tADSS tADSH
tKL
ADSP#
tADSS tADSH
ADSC#
tAS tAH
Deselect Cycle (Note 4) A2
tWS tWH
ADDRESS
A1
BWE#, GW#, BWa#-BWd#
tCES tCEH
CE# (NOTE 2) ADV#
tAAS
tAAH
ADV# suspends burst. OE#
t OEQ t KQLZ t OEHZ t OELZ tKQ tKQX t KQHZ
Q
High-Z
Q(A1)
t KQ
Q(A2)
Q(A2 + 1) (NOTE 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Single READ
BURST READ
Burst wraps around to its initial state.
DONOT CARE
UNDEFINED
READ TIMING PARAMETERS
-7.5 SYM
tKC fKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ
-8.5 MIN 10.0 113 100 1.9 1.9 7.5 8.5 3.0 4.0 4.2 4.2 5.0 5.0 0 4.2 5.0 0 3.0 4.0 4.0 4.0 MAX MIN 15
-10 MAX 66 UNITS ns MHz ns ns ns ns ns ns ns ns ns SYM tAS
tADSS tAAS tWS tCES tAH tADSH tAAH tWH tCEH
MIN 8.8 1.9 1.9 1.5 1.5
MAX
-7.5 MIN MAX 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5
-8.5 MIN MAX 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5
-10 MIN 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 MAX UNITS ns ns ns ns ns ns ns ns ns ns
10.0
5.0 5.0 5.0
0
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. 4. Outputs are disabled tKQHZ after deselect.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
WRITE TIMING
tKC
CLK
tKH tADSS tADSH
tKL
ADSP#
ADSC# extends burst.
tADSS tADSH tADSS tADSH
ADSC#
tAS tAH
ADDRESS
A1
A2
BYTE WRITE signals are ignored when ADSP# is LOW.
A3
tWS tWH
BWE#, BWa#-BWd# (NOTE 5) GW#
tCES tCEH tWS tWH
CE# (NOTE 2) ADV# (NOTE 4) OE# (NOTE 3)
tDS tDH
tAAS tAAH
ADV# suspends burst.
D
High-Z
tOEHZ
D(A1)
D(A2)
D(A2 + 1) (NOTE 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Q BURST READ Single WRITE BURST WRITE Extended BURST WRITE DONOT CARE UNDEFINED
WRITE TIMING PARAMETERS
-7.5 SYM tKC
fKF tKH tKL tOEHZ tAS tADSS tAAS tWS
-8.5 MIN 10.0 1.9 1.9 4.2 5.0 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 MAX 100 4.0 4.0 MIN 15
-10 MAX 66 UNITS ns MHz ns ns ns ns ns ns ns SYM tDS
tCES tAH tADSH tAAH tWH tDH tCEH
MIN 8.8 1.9 1.9 2.0 2.0 2.0 2.0
MAX 113
-7.5 MIN MAX 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5
-8.5 MIN MAX 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5
-10 MIN 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 MAX UNITS ns ns ns ns ns ns ns ns
5.0
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/ output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for the x18 version; or GW# HIGH and BWE#, BWa#-BWd# LOW for the x32 and x36 versions.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
READ/WRITE TIMING
tKC
CLK
tKH tADSS tADSH tKL
ADSP#
ADSC#
tAS tAH
ADDRESS
A1
A2
A3
tWS tWH
A4
A5
A6
BWE#, BWa#-BWd# (NOTE 4) CE# (NOTE 2)
tCES
tCEH
ADV#
OE#
tDS tDH tOELZ
D
High-Z
tOEHZ
D(A3)
tKQ
D(A5) (NOTE 1) Q(A4+1) Q(A4+2) Q(A4+3)
D(A6)
Q
Q(A1)
Q(A2) Single WRITE
Q(A4)
Back-to-Back READs
BURST READ
Back-to-Back WRITEs DONOT CARE UNDEFINED
READ/WRITE TIMING PARAMETERS
-7.5 MIN MAX 8.8 113 1.9 1.9 7.5 0 4.2 2.0 2.0 2.0 2.0 0 5.0 2.5 2.5 -8.5 MIN MAX 10.0 100 1.9 1.9 8.5 0 5.0 -10 MIN 15 4.0 4.0 10.0 MAX 66 UNITS ns MHz ns ns ns ns ns ns ns SYM tWS tDS
tCES tAH tADSH tWH tDH tCEH
SYM tKC fKF
tKH tKL tKQ tOELZ tOEHZ tAS tADSS
-7.5 MIN MAX 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5
-8.5 MIN MAX 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5
-10 MIN 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 MAX UNITS ns ns ns ns ns ns ns ns
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
PIN #1 ID 0.15
+0.03 -0.02
0.32
+0.06 -0.10
22.10
+0.10 -0.15
0.65
20.10 0.10 DETAIL A
0.62 14.00 0.10 +0.20 -0.05 GAGE PLANE
1.50 0.10 0.10
16.00
0.25
0.10
+0.10 -0.05
1.00 (TYP) 0.60 0.15 DETAIL A
1.40 0.05
NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. SyncBurst is a trademark of Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM MT58L64L18F.p65 - Rev. 9/99
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.

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